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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-07 11:01:16 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-07 11:07:08 -0500 |
| commit | 78b30a54c97882740d5b12a85247bf1d2e86f0e2 (patch) | |
| tree | 260d4a63b78c9de41d4f1d9e0de2f5b54c93050c /llvm/lib/Target/AMDGPU | |
| parent | 9daa44c9935053508b38d0203ac47130c8156b02 (diff) | |
| download | bcm5719-llvm-78b30a54c97882740d5b12a85247bf1d2e86f0e2.tar.gz bcm5719-llvm-78b30a54c97882740d5b12a85247bf1d2e86f0e2.zip | |
AMDGPU/GlobalISel: Fix readfirstlane pattern import
The imm folding optimization pattern failed to import. The instruction
pattern was already working, but failing to fail on SGPR inputs.
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOP1Instructions.td | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index dad0b8b2c0c..dcc139a9fe9 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1938,7 +1938,7 @@ def : GCNPat< // the ignored src1. def : GCNPat< (int_amdgcn_readfirstlane (i32 imm:$src)), - (S_MOV_B32 $src) + (S_MOV_B32 SReg_32:$src) >; multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> { diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td index 2d8f488168c..c7aed098554 100644 --- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td @@ -156,7 +156,7 @@ def V_READFIRSTLANE_B32 : InstSI <(outs SReg_32:$vdst), (ins VRegOrLds_32:$src0), "v_readfirstlane_b32 $vdst, $src0", - [(set i32:$vdst, (int_amdgcn_readfirstlane i32:$src0))]>, + [(set i32:$vdst, (int_amdgcn_readfirstlane (i32 VRegOrLds_32:$src0)))]>, Enc32 { let isCodeGenOnly = 0; |
