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| author | Ryan Taylor <rtayl@amd.com> | 2019-06-26 17:34:57 +0000 |
|---|---|---|
| committer | Ryan Taylor <rtayl@amd.com> | 2019-06-26 17:34:57 +0000 |
| commit | 9ab812d4752b2a1442426db2ccc17dc95d12eb04 (patch) | |
| tree | 1b9439a3630c4fcf053184b1e3d54c61bf7acd66 /llvm/lib/Target/AMDGPU/Utils | |
| parent | 4c86dd903265be9fd72a5ebf7c568a15f3cad0a6 (diff) | |
| download | bcm5719-llvm-9ab812d4752b2a1442426db2ccc17dc95d12eb04.tar.gz bcm5719-llvm-9ab812d4752b2a1442426db2ccc17dc95d12eb04.zip | |
[AMDGPU] Fix for branch offset hardware workaround
Summary:
This fixes a hardware bug that makes a branch offset of 0x3f unsafe.
This replaces the 32 bit branch with offset 0x3f to a 64 bit
instruction that includes the same 32 bit branch and the encoding
for a s_nop 0 to follow. The relaxer than modifies the offsets
accordingly.
Change-Id: I10b7aed99d651f8159401b01bb421f105fa6288e
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63494
llvm-svn: 364451
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Utils')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index b56dad808f4..5497fe195e2 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -190,6 +190,9 @@ unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs, LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx); +LLVM_READONLY +int getSOPPWithRelaxation(uint16_t Opcode); + struct MIMGBaseOpcodeInfo { MIMGBaseOpcode BaseOpcode; bool Store; |
