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authorTom Stellard <thomas.stellard@amd.com>2016-01-20 00:13:22 +0000
committerTom Stellard <thomas.stellard@amd.com>2016-01-20 00:13:22 +0000
commit2e045bbc5f1001a908bfb9267b792bdc6dd72c5d (patch)
tree008350af964d2965d3d1f18fa9bb3a7bf95927b8 /llvm/lib/Target/AMDGPU/SIISelLowering.h
parent69005960400a84f3c8b03f173afdad79ccd1d4a0 (diff)
downloadbcm5719-llvm-2e045bbc5f1001a908bfb9267b792bdc6dd72c5d.tar.gz
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AMDGPU/SI: Prevent the DAGCombiner from creating setcc with i1 inputs
Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15035 llvm-svn: 258256
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.h')
-rw-r--r--llvm/lib/Target/AMDGPU/SIISelLowering.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index f01b2c0d09f..47aa16ada32 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -89,6 +89,8 @@ public:
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override;
+ bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
+
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
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