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| author | Tom Stellard <tstellar@redhat.com> | 2018-06-01 02:19:46 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2018-06-01 02:19:46 +0000 |
| commit | e43778895c94de58d1e5fece501abec4d0f595f3 (patch) | |
| tree | 3fc95fc2b98f8d9f7b12bdfe5bafaa307ae14253 /llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | |
| parent | f83d547989c2dab2353cafb4aafa3561e87449d1 (diff) | |
| download | bcm5719-llvm-e43778895c94de58d1e5fece501abec4d0f595f3.tar.gz bcm5719-llvm-e43778895c94de58d1e5fece501abec4d0f595f3.zip | |
AMDGPU/R600: Move intrinsics to IntrinsicsAMDGPU.td
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D47487
llvm-svn: 333720
Diffstat (limited to 'llvm/lib/Target/AMDGPU/R600ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp index e3768ae98b0..414b3960137 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -472,7 +472,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); switch (IntrinsicID) { - case AMDGPUIntrinsic::r600_store_swizzle: { + case Intrinsic::r600_store_swizzle: { SDLoc DL(Op); const SDValue Args[8] = { Chain, @@ -499,14 +499,14 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const EVT VT = Op.getValueType(); SDLoc DL(Op); switch (IntrinsicID) { - case AMDGPUIntrinsic::r600_tex: - case AMDGPUIntrinsic::r600_texc: { + case Intrinsic::r600_tex: + case Intrinsic::r600_texc: { unsigned TextureOp; switch (IntrinsicID) { - case AMDGPUIntrinsic::r600_tex: + case Intrinsic::r600_tex: TextureOp = 0; break; - case AMDGPUIntrinsic::r600_texc: + case Intrinsic::r600_texc: TextureOp = 1; break; default: @@ -536,7 +536,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const }; return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); } - case AMDGPUIntrinsic::r600_dot4: { + case Intrinsic::r600_dot4: { SDValue Args[8] = { DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), DAG.getConstant(0, DL, MVT::i32)), |
