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| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2019-05-17 13:17:48 +0000 |
|---|---|---|
| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2019-05-17 13:17:48 +0000 |
| commit | 43fcc79837cd6fdf3d003fe3812f7c5522f8c476 (patch) | |
| tree | 1ad21497c62de227d7348bb0ae849b2e4ddbcee6 /llvm/lib/Target/AMDGPU/MCTargetDesc | |
| parent | 1a02d30c87307b9330946a1feab91b14c3fa5e57 (diff) | |
| download | bcm5719-llvm-43fcc79837cd6fdf3d003fe3812f7c5522f8c476.tar.gz bcm5719-llvm-43fcc79837cd6fdf3d003fe3812f7c5522f8c476.zip | |
[AMDGPU][MC] Enabled expressions for most operands which accept integer values
See bug 40873: https://bugs.llvm.org/show_bug.cgi?id=40873
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D60768
llvm-svn: 361031
Diffstat (limited to 'llvm/lib/Target/AMDGPU/MCTargetDesc')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp index f2c666b31f6..4776a176be6 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp @@ -439,7 +439,13 @@ uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, Kind = FK_PCRel_4; else Kind = FK_Data_4; - Fixups.push_back(MCFixup::create(4, MO.getExpr(), Kind, MI.getLoc())); + + const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); + uint32_t Offset = Desc.getSize(); + assert(Offset == 4 || Offset == 8); + + Fixups.push_back( + MCFixup::create(Offset, MO.getExpr(), Kind, MI.getLoc())); } // Figure out the operand number, needed for isSrcOperand check |
