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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-02-27 20:26:57 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-02-27 20:26:57 +0000 |
| commit | 3a61985b2fe922ee7c94c0aa148fad046347829d (patch) | |
| tree | 2c8a3a6d5e4450fb7dd03f0535f7d827a210cd4d /llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | |
| parent | d6ebd07b8d1ba5fed46790e0246a2d0716c4b63b (diff) | |
| download | bcm5719-llvm-3a61985b2fe922ee7c94c0aa148fad046347829d.tar.gz bcm5719-llvm-3a61985b2fe922ee7c94c0aa148fad046347829d.zip | |
AMDGPU: More bits of frame index are known to be zero
The maximum private allocation for the whole GPU is 4G,
so the maximum possible index for a single workitem is the
maximum size divided by the smallest granularity for a dispatch.
This increases the number of known zero high bits, which
enables more offset folding. The maximum private size per
workitem with this is 128M but may be smaller still.
llvm-svn: 262153
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index fed46fe3715..96319151765 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -84,7 +84,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS, GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), HasSMemRealTime(false), Has16BitInsts(false), LDSBankCount(0), - IsaVersion(ISAVersion0_0_0), EnableHugeScratchBuffer(false), + IsaVersion(ISAVersion0_0_0), EnableSIScheduler(false), FrameLowering(nullptr), InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) { |
