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| author | Aaron Ballman <aaron@aaronballman.com> | 2016-03-30 21:30:00 +0000 |
|---|---|---|
| committer | Aaron Ballman <aaron@aaronballman.com> | 2016-03-30 21:30:00 +0000 |
| commit | ef0fe1eed827ba8f9c6d76200821dc24ec6f038f (patch) | |
| tree | 13991a9058526c1d5989e5c1ce9a1d2a4a6a50b4 /llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | |
| parent | 46ba31650e9eb5f95990adc240c7d1e925c57381 (diff) | |
| download | bcm5719-llvm-ef0fe1eed827ba8f9c6d76200821dc24ec6f038f.tar.gz bcm5719-llvm-ef0fe1eed827ba8f9c6d76200821dc24ec6f038f.zip | |
Silencing warnings from MSVC 2015 Update 2. All of these changes silence "C4334 '<<': result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)". NFC.
llvm-svn: 264929
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 5a17028e35c..855455e5c4c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -1447,7 +1447,7 @@ void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op, // Add LHS high bit REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit); - SDValue BIT = DAG.getConstant(1 << bitPos, DL, HalfVT); + SDValue BIT = DAG.getConstant(1ULL << bitPos, DL, HalfVT); SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE); DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT); |
