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authorTim Northover <tnorthover@apple.com>2013-07-01 14:48:48 +0000
committerTim Northover <tnorthover@apple.com>2013-07-01 14:48:48 +0000
commit953abab40ae89d546a379fa97afe6dea483e851a (patch)
tree5db8f9756cabd9087db5f0a5ed8455bab444769b /llvm/lib/Support/YAMLParser.cpp
parent8a4e24ea8b9d7059fa0a8b0a3ce3b838115dcc4a (diff)
downloadbcm5719-llvm-953abab40ae89d546a379fa97afe6dea483e851a.tar.gz
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ARM: relax the atomic release barrier to "dmb ishst"
I believe the full "dmb ish" barrier is not required to guarantee release semantics for atomic operations. The weaker "dmb ishst" prevents previous operations being reordered with a store executed afterwards, which is enough. A key point to note (fortunately already correct) is that this barrier alone is *insufficient* for sequential consistency, no matter how liberally placed. llvm-svn: 185339
Diffstat (limited to 'llvm/lib/Support/YAMLParser.cpp')
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