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authorDjordje Todorovic <djordje.todorovic@rt-rk.com>2019-06-27 13:52:34 +0000
committerDjordje Todorovic <djordje.todorovic@rt-rk.com>2019-06-27 13:52:34 +0000
commita0d45058ebb39dc18cbcdcba01d11d36eca001be (patch)
treea5a1d6c8bee81c6fd5322c99ec0887959905625f /llvm/lib/IR/DebugInfoMetadata.cpp
parentc692a8dc51de996eed2214379c368c93e9a5354b (diff)
downloadbcm5719-llvm-a0d45058ebb39dc18cbcdcba01d11d36eca001be.tar.gz
bcm5719-llvm-a0d45058ebb39dc18cbcdcba01d11d36eca001be.zip
[DWARF] Handle the DW_OP_entry_value operand
Add the IR and the AsmPrinter parts for handling of the DW_OP_entry_values DWARF operation. ([11/13] Introduce the debug entry values.) Co-authored-by: Ananth Sowda <asowda@cisco.com> Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com> Co-authored-by: Ivan Baev <ibaev@cisco.com> Differential Revision: https://reviews.llvm.org/D60866 llvm-svn: 364542
Diffstat (limited to 'llvm/lib/IR/DebugInfoMetadata.cpp')
-rw-r--r--llvm/lib/IR/DebugInfoMetadata.cpp21
1 files changed, 19 insertions, 2 deletions
diff --git a/llvm/lib/IR/DebugInfoMetadata.cpp b/llvm/lib/IR/DebugInfoMetadata.cpp
index 76d9ce3332c..1607cf5104f 100644
--- a/llvm/lib/IR/DebugInfoMetadata.cpp
+++ b/llvm/lib/IR/DebugInfoMetadata.cpp
@@ -836,6 +836,7 @@ unsigned DIExpression::ExprOperand::getSize() const {
case dwarf::DW_OP_deref_size:
case dwarf::DW_OP_plus_uconst:
case dwarf::DW_OP_LLVM_tag_offset:
+ case dwarf::DW_OP_entry_value:
return 2;
default:
return 1;
@@ -876,6 +877,13 @@ bool DIExpression::isValid() const {
return false;
break;
}
+ case dwarf::DW_OP_entry_value: {
+ // An entry value operator must appear at the begin and the size
+ // of following expression should be 1, because we support only
+ // entry values of a simple register location.
+ return I->get() == expr_op_begin()->get() && I->getArg(0) == 1 &&
+ getNumElements() == 2;
+ }
case dwarf::DW_OP_LLVM_convert:
case dwarf::DW_OP_LLVM_tag_offset:
case dwarf::DW_OP_constu:
@@ -994,15 +1002,24 @@ DIExpression *DIExpression::prepend(const DIExpression *Expr, uint8_t Flags,
Ops.push_back(dwarf::DW_OP_deref);
bool StackValue = Flags & DIExpression::StackValue;
+ bool EntryValue = Flags & DIExpression::EntryValue;
- return prependOpcodes(Expr, Ops, StackValue);
+ return prependOpcodes(Expr, Ops, StackValue, EntryValue);
}
DIExpression *DIExpression::prependOpcodes(const DIExpression *Expr,
SmallVectorImpl<uint64_t> &Ops,
- bool StackValue) {
+ bool StackValue,
+ bool EntryValue) {
assert(Expr && "Can't prepend ops to this expression");
+ if (EntryValue) {
+ Ops.push_back(dwarf::DW_OP_entry_value);
+ // Add size info needed for entry value expression.
+ // Add plus one for target register operand.
+ Ops.push_back(Expr->getNumElements() + 1);
+ }
+
// If there are no ops to prepend, do not even add the DW_OP_stack_value.
if (Ops.empty())
StackValue = false;
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