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authorJuergen Ributzka <juergen@apple.com>2014-08-19 19:44:17 +0000
committerJuergen Ributzka <juergen@apple.com>2014-08-19 19:44:17 +0000
commitb46ea081ad9fb228aabe19f7fdf7f6d74de8ccf3 (patch)
tree320858de046072a0f178d4bdcee3f49f28cc2aec /llvm/lib/IR/Constants.cpp
parente3698ab6e3dc4752e39677f38a5cbc19fe31af1c (diff)
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Reapply [FastISel][AArch64] Add support for more addressing modes (r215597).
Note: This was originally reverted to track down a buildbot error. Reapply without any modifications. Original commit message: FastISel didn't take much advantage of the different addressing modes available to it on AArch64. This commit allows the ComputeAddress method to recognize more addressing modes that allows shifts and sign-/zero-extensions to be folded into the memory operation itself. For Example: lsl x1, x1, #3 --> ldr x0, [x0, x1, lsl #3] ldr x0, [x0, x1] sxtw x1, w1 lsl x1, x1, #3 --> ldr x0, [x0, x1, sxtw #3] ldr x0, [x0, x1] llvm-svn: 216013
Diffstat (limited to 'llvm/lib/IR/Constants.cpp')
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