Simplify my (il)logic.

llvm-svn: 43819

1 files changed, 2 insertions, 11 deletions

diff --git a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
index 929b1e7e92d..5c4697850ae 100644
--- a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -316,6 +316,7 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, unsigned reg) {
         if (!mop.isRegister())
           continue;
         unsigned Reg = mop.getReg();
+        unsigned RegI = Reg;
         if (Reg == 0 || MRegisterInfo::isPhysicalRegister(Reg))
           continue;
         bool isSubReg = RegMap->isSubRegister(Reg);
@@ -381,17 +382,7 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, unsigned reg) {
           unsigned RegJ = MI->getOperand(j).getReg();
           if (RegJ == 0 || MRegisterInfo::isPhysicalRegister(RegJ))
             continue;
-          bool isSubRegJ = RegMap->isSubRegister(RegJ);
-          if (isSubRegJ) {
-            assert(!isSubReg || RegMap->getSubRegisterIndex(RegJ) == SubIdx);
-            RegJ = RegMap->getSuperRegister(RegJ);
-          }
-          // Important to check "isSubRegJ == isSubReg".
-          // e.g. %reg1024 = MOVSX32rr16 %reg1025. It's possible that both
-          // registers are coalesced to the same register but only %reg1025 is
-          // a sub-register use. They should not be rewritten to the same
-          // register.
-          if (RegJ == li.reg && isSubRegJ == isSubReg) {
+          if (RegJ == RegI) {
             MI->getOperand(j).setReg(NewVReg);
             HasUse |= MI->getOperand(j).isUse();
             HasDef |= MI->getOperand(j).isDef();