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| author | Craig Topper <craig.topper@intel.com> | 2017-07-31 17:35:44 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-07-31 17:35:44 +0000 |
| commit | cb0e74975a516d1fbc83e674c36e4cca3fee7731 (patch) | |
| tree | cdb0c6e1ea2ac97a840ff0ee08c7f7594e21c33f /llvm/lib/CodeGen | |
| parent | ed99e4c5b2b881ec906e748dbd579d7ee75bc6eb (diff) | |
| download | bcm5719-llvm-cb0e74975a516d1fbc83e674c36e4cca3fee7731.tar.gz bcm5719-llvm-cb0e74975a516d1fbc83e674c36e4cca3fee7731.zip | |
[AVX-512] Remove patterns that select vmovdqu8/16 for unmasked loads. Prefer vmovdqa64/vmovdqu64 instead.
These were taking priority over the aligned load instructions since there is no vmovda8/16. I don't think there is really a difference between aligned and unaligned on newer cpus so I don't think it matters which instructions we use.
But with this change we reduce the size of the isel table a little and we allow the aligned information to pass through to the evex->vec pass and produce the same output has avx/avx2 in some cases.
I also generally dislike patterns rooted in a bitcast which these were.
Differential Revision: https://reviews.llvm.org/D35977
llvm-svn: 309589
Diffstat (limited to 'llvm/lib/CodeGen')
0 files changed, 0 insertions, 0 deletions
