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authorNico Weber <nicolasweber@gmx.de>2019-05-03 18:08:03 +0000
committerNico Weber <nicolasweber@gmx.de>2019-05-03 18:08:03 +0000
commitbb852a96723aaa86d23c58e445fd05bbda979bbd (patch)
tree7ff5b3a99a5fbae6c66bc4bca64d7ef0f3a02703 /llvm/lib/CodeGen
parent308b5ec1ff476710a83bd0ab2d6490a20d8f4f38 (diff)
downloadbcm5719-llvm-bb852a96723aaa86d23c58e445fd05bbda979bbd.tar.gz
bcm5719-llvm-bb852a96723aaa86d23c58e445fd05bbda979bbd.zip
Revert r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
Makes clang/test/Misc/backend-stack-frame-diagnostics-fallback.cpp fail. llvm-svn: 359912
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/RegAllocFast.cpp45
1 files changed, 4 insertions, 41 deletions
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index c11ae9cce1a..a711db1c0eb 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -101,10 +101,6 @@ namespace {
DenseMap<unsigned, SmallVector<MachineInstr *, 2>> LiveDbgValueMap;
- /// Has a bit set for every virtual register for which it was determined
- /// that it is alive across blocks.
- BitVector MayLiveAcrossBlocks;
-
/// State of a physical register.
enum RegState {
/// A disabled register is not available for allocation, but an alias may
@@ -212,7 +208,7 @@ namespace {
unsigned Hint);
LiveReg &reloadVirtReg(MachineInstr &MI, unsigned OpNum, unsigned VirtReg,
unsigned Hint);
- void spillAll(MachineBasicBlock::iterator MI, bool OnlyLiveOut);
+ void spillAll(MachineBasicBlock::iterator MI);
bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
int getStackSpaceFor(unsigned VirtReg);
@@ -221,8 +217,6 @@ namespace {
void reload(MachineBasicBlock::iterator Before, unsigned VirtReg,
MCPhysReg PhysReg);
- bool mayLiveOut(unsigned VirtReg);
-
void dumpState();
};
@@ -257,33 +251,6 @@ int RegAllocFast::getStackSpaceFor(unsigned VirtReg) {
return FrameIdx;
}
-/// Returns false if \p VirtReg is known to not live out of the current block.
-bool RegAllocFast::mayLiveOut(unsigned VirtReg) {
- if (MayLiveAcrossBlocks.test(TargetRegisterInfo::virtReg2Index(VirtReg))) {
- // Cannot be live-out if there are no successors.
- return !MBB->succ_empty();
- }
-
- // If this block loops back to itself, it would be necessary to check whether
- // the use comes after the def.
- if (MBB->isSuccessor(MBB))
- return true;
-
- // See if the first \p Limit uses of the register are all in the current
- // block.
- static const unsigned Limit = 8;
- unsigned C = 0;
- for (const MachineInstr &UseInst : MRI->reg_nodbg_instructions(VirtReg)) {
- if (UseInst.getParent() != MBB || ++C >= Limit) {
- MayLiveAcrossBlocks.set(TargetRegisterInfo::virtReg2Index(VirtReg));
- // Cannot be live-out if there are no successors.
- return !MBB->succ_empty();
- }
- }
-
- return false;
-}
-
/// Insert spill instruction for \p AssignedReg before \p Before. Update
/// DBG_VALUEs with \p VirtReg operands with the stack slot.
void RegAllocFast::spill(MachineBasicBlock::iterator Before, unsigned VirtReg,
@@ -407,7 +374,7 @@ void RegAllocFast::spillVirtReg(MachineBasicBlock::iterator MI, LiveReg &LR) {
}
/// Spill all dirty virtregs without killing them.
-void RegAllocFast::spillAll(MachineBasicBlock::iterator MI, bool OnlyLiveOut) {
+void RegAllocFast::spillAll(MachineBasicBlock::iterator MI) {
if (LiveVirtRegs.empty())
return;
// The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
@@ -415,8 +382,6 @@ void RegAllocFast::spillAll(MachineBasicBlock::iterator MI, bool OnlyLiveOut) {
for (LiveReg &LR : LiveVirtRegs) {
if (!LR.PhysReg)
continue;
- if (OnlyLiveOut && !mayLiveOut(LR.VirtReg))
- continue;
spillVirtReg(MI, LR);
}
LiveVirtRegs.clear();
@@ -1054,7 +1019,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
// definitions may be used later on and we do not want to reuse
// those for virtual registers in between.
LLVM_DEBUG(dbgs() << " Spilling remaining registers before call.\n");
- spillAll(MI, /*OnlyLiveOut*/ false);
+ spillAll(MI);
}
// Third scan.
@@ -1164,7 +1129,7 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) {
// Spill all physical registers holding virtual registers now.
LLVM_DEBUG(dbgs() << "Spilling live registers at end of block.\n");
- spillAll(MBB.getFirstTerminator(), /*OnlyLiveOut*/ true);
+ spillAll(MBB.getFirstTerminator());
// Erase all the coalesced copies. We are delaying it until now because
// LiveVirtRegs might refer to the instrs.
@@ -1193,8 +1158,6 @@ bool RegAllocFast::runOnMachineFunction(MachineFunction &MF) {
unsigned NumVirtRegs = MRI->getNumVirtRegs();
StackSlotForVirtReg.resize(NumVirtRegs);
LiveVirtRegs.setUniverse(NumVirtRegs);
- MayLiveAcrossBlocks.clear();
- MayLiveAcrossBlocks.resize(NumVirtRegs);
// Loop over all of the basic blocks, eliminating virtual register references
for (MachineBasicBlock &MBB : MF)
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