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authorEvan Cheng <evan.cheng@apple.com>2006-12-15 22:42:55 +0000
committerEvan Cheng <evan.cheng@apple.com>2006-12-15 22:42:55 +0000
commit884bc09d10d2df36aa5ff22ca847a2f5586e0f62 (patch)
treee7b0f6b88d58ccd7fea1cf83efe553acbae9aa46 /llvm/lib/CodeGen
parent75e93bc8c77703c84d19ff6fb4efcd0910ba124e (diff)
downloadbcm5719-llvm-884bc09d10d2df36aa5ff22ca847a2f5586e0f62.tar.gz
bcm5719-llvm-884bc09d10d2df36aa5ff22ca847a2f5586e0f62.zip
Fix select_cc, select expansion to soft-fp bugs.
llvm-svn: 32616
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp14
1 files changed, 11 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 49ebec0b3ba..09ba005ea7e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -4705,18 +4705,24 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
SDOperand LL, LH, RL, RH;
ExpandOp(Node->getOperand(1), LL, LH);
ExpandOp(Node->getOperand(2), RL, RH);
+ if (getTypeAction(NVT) == Expand)
+ NVT = TLI.getTypeToExpandTo(NVT);
Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
- Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
+ if (VT != MVT::f32)
+ Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
break;
}
case ISD::SELECT_CC: {
SDOperand TL, TH, FL, FH;
ExpandOp(Node->getOperand(2), TL, TH);
ExpandOp(Node->getOperand(3), FL, FH);
+ if (getTypeAction(NVT) == Expand)
+ NVT = TLI.getTypeToExpandTo(NVT);
Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
Node->getOperand(1), TL, FL, Node->getOperand(4));
- Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
- Node->getOperand(1), TH, FH, Node->getOperand(4));
+ if (VT != MVT::f32)
+ Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
+ Node->getOperand(1), TH, FH, Node->getOperand(4));
break;
}
case ISD::ANY_EXTEND:
@@ -4761,6 +4767,8 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
// f32 / f64 must be expanded to i32 / i64.
if (VT == MVT::f32 || VT == MVT::f64) {
Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
+ if (getTypeAction(NVT) == Expand)
+ ExpandOp(Lo, Lo, Hi);
break;
}
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