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authorChris Lattner <sabre@nondot.org>2007-03-06 20:01:06 +0000
committerChris Lattner <sabre@nondot.org>2007-03-06 20:01:06 +0000
commit13780ac7dbb04e929949f05c48be0fec3559c5c6 (patch)
tree0340e41d194be3f4959328360bb871480f0efa9a /llvm/lib/CodeGen
parentdb0db9740b0cf5ff7cd7d2d4152b8361024577ad (diff)
downloadbcm5719-llvm-13780ac7dbb04e929949f05c48be0fec3559c5c6.tar.gz
bcm5719-llvm-13780ac7dbb04e929949f05c48be0fec3559c5c6.zip
big endian 32-bit systems (e.g. ppc32) want to return the high reg first, not
the lo-reg first. This is fallout from my ppc calling conv change yesterday, it fixes test/ExecutionEngine/2003-05-06-LivenessClobber.llx llvm-svn: 34983
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 84a381bf633..8c90cfb6dac 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1675,6 +1675,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
if (Tmp2.getValueType() != MVT::Vector) {
SDOperand Lo, Hi;
ExpandOp(Tmp2, Lo, Hi);
+
+ // Big endian systems want the hi reg first.
+ if (!TLI.isLittleEndian())
+ std::swap(Lo, Hi);
+
if (Hi.Val)
Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
else
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