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| author | Chris Lattner <sabre@nondot.org> | 2006-05-04 18:05:43 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-05-04 18:05:43 +0000 |
| commit | 10b71c0d08095e256aa3ed8e088abb41087ca24e (patch) | |
| tree | 8f68c2d63e5d29943fce5b09763c105b36f36a0e /llvm/lib/CodeGen | |
| parent | 700cd27e834f6bb2a2af98c08edf82de487361a3 (diff) | |
| download | bcm5719-llvm-10b71c0d08095e256aa3ed8e088abb41087ca24e.tar.gz bcm5719-llvm-10b71c0d08095e256aa3ed8e088abb41087ca24e.zip | |
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
llvm-svn: 28104
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/MachineInstr.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index b1fb52a13a5..f2a604cf6d0 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -138,7 +138,7 @@ static void print(const MachineOperand &MO, std::ostream &OS, if (TM) MRI = TM->getRegisterInfo(); switch (MO.getType()) { - case MachineOperand::MO_VirtualRegister: + case MachineOperand::MO_Register: OutputReg(OS, MO.getReg(), MRI); break; case MachineOperand::MO_Immediate: @@ -235,7 +235,7 @@ std::ostream &llvm::operator<<(std::ostream &os, const MachineInstr &MI) { std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) { switch (MO.getType()) { - case MachineOperand::MO_VirtualRegister: + case MachineOperand::MO_Register: OutputReg(OS, MO.getReg()); break; case MachineOperand::MO_Immediate: diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 2b7b877cb17..cf1227964a5 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -104,7 +104,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, } } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { - MI->addZeroExtImm64Operand(C->getValue()); + MI->addImmOperand(C->getValue()); } else if (RegisterSDNode*R = dyn_cast<RegisterSDNode>(Op)) { MI->addRegOperand(R->getReg(), MachineOperand::Use); @@ -303,7 +303,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue(); unsigned NumVals = Flags >> 3; - MI->addZeroExtImm64Operand(Flags); + MI->addImmOperand(Flags); ++i; // Skip the ID value. switch (Flags & 7) { @@ -323,7 +323,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, case 3: { // Immediate. assert(NumVals == 1 && "Unknown immediate value!"); uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue(); - MI->addZeroExtImm64Operand(Val); + MI->addImmOperand(Val); ++i; break; } |
