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authorChris Lattner <sabre@nondot.org>2007-12-22 21:26:52 +0000
committerChris Lattner <sabre@nondot.org>2007-12-22 21:26:52 +0000
commitafc8f13bf5c620459e5891b3b95271b071c2f15b (patch)
tree122b57664ff1386eed4b55ca10356072f13e08cb /llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
parentefd1cddb5ab34561b97d184b7e3fd590799fe0f3 (diff)
downloadbcm5719-llvm-afc8f13bf5c620459e5891b3b95271b071c2f15b.tar.gz
bcm5719-llvm-afc8f13bf5c620459e5891b3b95271b071c2f15b.zip
improve support for fgetsign
llvm-svn: 45322
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp6
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index cbeda67727a..ba0a08bd8cf 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1323,6 +1323,11 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
KnownZero |= (~InMask) & Mask;
return;
}
+ case ISD::FGETSIGN:
+ // All bits are zero except the low bit.
+ KnownZero = MVT::getIntVTBitMask(Op.getValueType()) ^ 1;
+ return;
+
case ISD::ADD: {
// If either the LHS or the RHS are Zero, the result is zero.
ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
@@ -3703,6 +3708,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::FDIV: return "fdiv";
case ISD::FREM: return "frem";
case ISD::FCOPYSIGN: return "fcopysign";
+ case ISD::FGETSIGN: return "fgetsign";
case ISD::SETCC: return "setcc";
case ISD::SELECT: return "select";
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