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| author | Eric Christopher <echristo@gmail.com> | 2014-10-08 07:32:17 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@gmail.com> | 2014-10-08 07:32:17 +0000 |
| commit | b17140de3509418d5c383a6ad131ad812f833f0a (patch) | |
| tree | 5d02a573850f3f1946a3c1cc1858c91d2ac83223 /llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp | |
| parent | 1b3b70e371d10ec9a1272bd10f7e08d43e63b511 (diff) | |
| download | bcm5719-llvm-b17140de3509418d5c383a6ad131ad812f833f0a.tar.gz bcm5719-llvm-b17140de3509418d5c383a6ad131ad812f833f0a.zip | |
Cache TargetLowering on SelectionDAGISel and update previous
calls to getTargetLowering() with the cached variable.
llvm-svn: 219284
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp b/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp index aaf1e1fe050..c59a3005523 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp @@ -42,13 +42,12 @@ static cl::opt<signed> RegPressureThreshold( cl::desc("Track reg pressure and switch priority to in-depth")); ResourcePriorityQueue::ResourcePriorityQueue(SelectionDAGISel *IS) - : Picker(this), InstrItins(IS->getTargetLowering() - ->getTargetMachine() + : Picker(this), InstrItins(IS->TLI->getTargetMachine() .getSubtargetImpl() ->getInstrItineraryData()) { const TargetMachine &TM = (*IS->MF).getTarget(); TRI = TM.getSubtargetImpl()->getRegisterInfo(); - TLI = IS->getTargetLowering(); + TLI = IS->TLI; TII = TM.getSubtargetImpl()->getInstrInfo(); ResourcesModel = TII->CreateTargetScheduleState(&TM, nullptr); // This hard requirement could be relaxed, but for now |

