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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2014-11-19 10:06:49 +0000 |
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| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2014-11-19 10:06:49 +0000 |
| commit | 3ac3b251a96e1e99e3aebcf9d99da16682483f6f (patch) | |
| tree | 0cc5f690e72c8f94951094d49954829274ab8254 /llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | |
| parent | 59229dcb290d6503ef9c4ae1bff2933325b86d0a (diff) | |
| download | bcm5719-llvm-3ac3b251a96e1e99e3aebcf9d99da16682483f6f.tar.gz bcm5719-llvm-3ac3b251a96e1e99e3aebcf9d99da16682483f6f.zip | |
[X86][SSE] pslldq/psrldq byte shifts/rotation for SSE2
This patch builds on http://reviews.llvm.org/D5598 to perform byte rotation shuffles (lowerVectorShuffleAsByteRotate) on pre-SSSE3 (palignr) targets - pre-SSSE3 is only enabled on i8 and i16 vector targets where it is a more definite performance gain.
I've also added a separate byte shift shuffle (lowerVectorShuffleAsByteShift) that makes use of the ability of the SLLDQ/SRLDQ instructions to implicitly shift in zero bytes to avoid the need to create a zero register if we had used palignr.
Differential Revision: http://reviews.llvm.org/D5699
llvm-svn: 222340
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
0 files changed, 0 insertions, 0 deletions
