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| author | James Molloy <james.molloy@arm.com> | 2015-05-15 09:03:15 +0000 |
|---|---|---|
| committer | James Molloy <james.molloy@arm.com> | 2015-05-15 09:03:15 +0000 |
| commit | 7e9776b55949f8fdbfdee1a66ec8aa04289436bc (patch) | |
| tree | c7a7770e280255a6504f9a7e17f7e1a502b5d823 /llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | |
| parent | f0ab553fea2e01effa387ead1ae71e774f0793ab (diff) | |
| download | bcm5719-llvm-7e9776b55949f8fdbfdee1a66ec8aa04289436bc.tar.gz bcm5719-llvm-7e9776b55949f8fdbfdee1a66ec8aa04289436bc.zip | |
Add SDNodes for umin, umax, smin and smax.
This adds new SDNodes for signed/unsigned min/max. These nodes are built from
select/icmp pairs matched at SDAGBuilder stage.
This patch adds the nodes, as well as legalization support and sets them to
be "expand" for all targets.
NFC for now; this will be tested when I switch AArch64 to using these new
nodes.
llvm-svn: 237423
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 11b7d7069d7..c06227bd970 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -322,6 +322,10 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) { case ISD::ANY_EXTEND_VECTOR_INREG: case ISD::SIGN_EXTEND_VECTOR_INREG: case ISD::ZERO_EXTEND_VECTOR_INREG: + case ISD::SMIN: + case ISD::SMAX: + case ISD::UMIN: + case ISD::UMAX: QueryType = Node->getValueType(0); break; case ISD::FP_ROUND_INREG: |
