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| author | Nirav Dave <niravd@google.com> | 2016-06-22 19:03:26 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2016-06-22 19:03:26 +0000 |
| commit | 96beb7dee54e2e6cb6b28ea4bb90afd2f2f55d86 (patch) | |
| tree | a934b577178c3a7f7bcf0f6994c0ce29629e6199 /llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | |
| parent | 0526e7f8d907840f1aa600ee366006eec3ecba4f (diff) | |
| download | bcm5719-llvm-96beb7dee54e2e6cb6b28ea4bb90afd2f2f55d86.tar.gz bcm5719-llvm-96beb7dee54e2e6cb6b28ea4bb90afd2f2f55d86.zip | |
Preserve DebugInfo when replacing values in DAGCombiner
Recommiting after fixing over-aggressive assertion
[DAG] Previously debug values would transfer debuginfo for the selected
start node for a replacement which allows for debug to be dropped.
Push debug value transfer to occur with node/value replacement in
SelectionDAG, remove now extraneous transfers of debug values.
This refixes PR9817 which was being incompletely checked in the
testsuite.
Reviewers: jyknight
Subscribers: dblaikie, llvm-commits
Differential Revision: http://reviews.llvm.org/D21037
llvm-svn: 273456
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 4448b0582ba..a44b936ba92 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -320,7 +320,6 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, "Chain and glue operands should occur at end of operand list!"); // Get/emit the operand. unsigned VReg = getVR(Op, VRBaseMap); - assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); const MCInstrDesc &MCID = MIB->getDesc(); bool isOptDef = IIOpNum < MCID.getNumOperands() && @@ -334,6 +333,8 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, const TargetRegisterClass *DstRC = nullptr; if (IIOpNum < II->getNumOperands()) DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); + assert((!DstRC || TargetRegisterInfo::isVirtualRegister(VReg)) && + "Expected VReg"); if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { unsigned NewVReg = MRI->createVirtualRegister(DstRC); BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), |
