diff options
| author | Andrew Trick <atrick@apple.com> | 2013-04-13 06:07:40 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-04-13 06:07:40 +0000 |
| commit | e833e1cd6eeb722edbb5c5f316fbca16abd384c9 (patch) | |
| tree | 66678682e05b7164c4b9770c298946ee7648c502 /llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | |
| parent | 52b8387fd1755ab578daa7185199e8979d525fae (diff) | |
| download | bcm5719-llvm-e833e1cd6eeb722edbb5c5f316fbca16abd384c9.tar.gz bcm5719-llvm-e833e1cd6eeb722edbb5c5f316fbca16abd384c9.zip | |
MI-Sched: schedule physreg copies.
The register allocator expects minimal physreg live ranges. Schedule
physreg copies accordingly. This is slightly tricky when they occur in
the middle of the scheduling region. For now, this is handled by
rescheduling the copy when its associated instruction is
scheduled. Eventually we may instead bundle them, but only if we can
preserve the bundles as parallel copies during regalloc.
llvm-svn: 179449
Diffstat (limited to 'llvm/lib/CodeGen/ScheduleDAGInstrs.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp index 71e7a21ef2b..e4da6a41eea 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -262,6 +262,9 @@ void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { if (UseOp < 0) Dep = SDep(SU, SDep::Artificial); else { + // Set the hasPhysRegDefs only for physreg defs that have a use within + // the scheduling region. + SU->hasPhysRegDefs = true; Dep = SDep(SU, SDep::Data, *Alias); RegUse = UseSU->getInstr(); Dep.setMinLatency( @@ -318,6 +321,7 @@ void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { } if (!MO.isDef()) { + SU->hasPhysRegUses = true; // Either insert a new Reg2SUnits entry with an empty SUnits list, or // retrieve the existing SUnits list for this register's uses. // Push this SUnit on the use list. |

