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authorEugene Zelenko <eugene.zelenko@gmail.com>2017-02-21 22:07:52 +0000
committerEugene Zelenko <eugene.zelenko@gmail.com>2017-02-21 22:07:52 +0000
commit49e2fc4f5f043a4437d793771d595220d98b3b37 (patch)
tree39210a76e02e15a7f443033a6b277fd0590a106b /llvm/lib/CodeGen/RegisterClassInfo.cpp
parentf9e8034c9cbf63be932c757a9e2fd3b96c3c5046 (diff)
downloadbcm5719-llvm-49e2fc4f5f043a4437d793771d595220d98b3b37.tar.gz
bcm5719-llvm-49e2fc4f5f043a4437d793771d595220d98b3b37.zip
[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 295773
Diffstat (limited to 'llvm/lib/CodeGen/RegisterClassInfo.cpp')
-rw-r--r--llvm/lib/CodeGen/RegisterClassInfo.cpp18
1 files changed, 13 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp
index e93766ec01b..e61831b151d 100644
--- a/llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -1,4 +1,4 @@
-//===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
+//===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -14,12 +14,21 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/RegisterClassInfo.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegisterClassInfo.h"
+#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
using namespace llvm;
@@ -29,8 +38,7 @@ static cl::opt<unsigned>
StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
cl::desc("Limit all regclasses to N registers"));
-RegisterClassInfo::RegisterClassInfo()
- : Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {}
+RegisterClassInfo::RegisterClassInfo() = default;
void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
bool Update = false;
@@ -114,7 +122,7 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
}
}
RCI.NumRegs = N + CSRAlias.size();
- assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
+ assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
// CSR aliases go after the volatile registers, preserve the target's order.
for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
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