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| author | Alp Toker <alp@nuanti.com> | 2014-02-25 04:21:15 +0000 |
|---|---|---|
| committer | Alp Toker <alp@nuanti.com> | 2014-02-25 04:21:15 +0000 |
| commit | 70b36995e4cb090a922b6f2a96c7fe507506c0b3 (patch) | |
| tree | 7a12ecc48efc87b2494e50213f3d60faa9816429 /llvm/lib/CodeGen/RegAllocGreedy.cpp | |
| parent | 83cee7722d884090a7e91ffe397c43f97be2e5f8 (diff) | |
| download | bcm5719-llvm-70b36995e4cb090a922b6f2a96c7fe507506c0b3.tar.gz bcm5719-llvm-70b36995e4cb090a922b6f2a96c7fe507506c0b3.zip | |
Fix typos
llvm-svn: 202107
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocGreedy.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocGreedy.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index 3c3f622759f..21e23df1073 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -1916,7 +1916,7 @@ RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg, /// R3 is available. /// Recoloring => vC = R1, vA = R2, vB = R3 /// -/// \p Order defines the prefered allocation order for \p VirtReg. +/// \p Order defines the preferred allocation order for \p VirtReg. /// \p NewRegs will contain any new virtual register that have been created /// (split, spill) during the process and that must be assigned. /// \p FixedRegisters contains all the virtual registers that cannot be |
