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| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-01-18 14:17:50 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-01-18 14:17:50 +0000 |
| commit | 517b61cb69d6cf19841c07242dc1c7dc901736c4 (patch) | |
| tree | 735cbd5226c4be53ca4d0f41337cf1f8936563a8 /llvm/lib/CodeGen/PrologEpilogInserter.cpp | |
| parent | df7c6ef96fde9369baf4cdd5a343088e5b3e65cc (diff) | |
| download | bcm5719-llvm-517b61cb69d6cf19841c07242dc1c7dc901736c4.tar.gz bcm5719-llvm-517b61cb69d6cf19841c07242dc1c7dc901736c4.zip | |
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since last commit:
The new tablegen pass is now correctly guarded by LLVM_BUILD_GLOBAL_ISEL and
this should fix the buildbots however it may not be the whole fix. The previous
buildbot failures suggest there may be a memory bug lurking that I'm unable to
reproduce (including when using asan) or spot in the source. If they re-occur
on this commit then I'll need assistance from the bot owners to track it down.
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292367
Diffstat (limited to 'llvm/lib/CodeGen/PrologEpilogInserter.cpp')
0 files changed, 0 insertions, 0 deletions
