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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-08-01 17:51:20 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-08-01 17:51:20 +0000 |
| commit | 486072d3d6e1885eb3458e26cb23c2e9d6f91571 (patch) | |
| tree | c47958dc36f881b155d20891dfe78c446b0084ff /llvm/lib/CodeGen/PostRASchedulerList.cpp | |
| parent | 4115b361006913cee656f90ff3e63053455f9f30 (diff) | |
| download | bcm5719-llvm-486072d3d6e1885eb3458e26cb23c2e9d6f91571.tar.gz bcm5719-llvm-486072d3d6e1885eb3458e26cb23c2e9d6f91571.zip | |
[X86][SSE] Added missing vector logic intrinsic schedules
Improves atom scheduler test coverage (to make it easier to upgrade them for PR32431).
Merged SSE_VEC_BIT_ITINS_P + SSE_BIT_ITINS_P as we were interchanging between them.
llvm-svn: 309715
Diffstat (limited to 'llvm/lib/CodeGen/PostRASchedulerList.cpp')
0 files changed, 0 insertions, 0 deletions
