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author | Matthias Braun <matze@braunis.de> | 2015-11-03 01:53:29 +0000 |
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committer | Matthias Braun <matze@braunis.de> | 2015-11-03 01:53:29 +0000 |
commit | 93563e703256e1b7c1c366f80bdd941de4c738ac (patch) | |
tree | eff3adb1e5351cd542b3497208a75ab8bc40e89b /llvm/lib/CodeGen/PostRASchedulerList.cpp | |
parent | c0d8f0ca7d8f620e19447856e88c1131c538be78 (diff) | |
download | bcm5719-llvm-93563e703256e1b7c1c366f80bdd941de4c738ac.tar.gz bcm5719-llvm-93563e703256e1b7c1c366f80bdd941de4c738ac.zip |
ScheduleDAGInstrs: Remove IsPostRA flag; NFC
ScheduleDAGInstrs doesn't behave differently before or after register
allocation. It was only used in a method of MachineSchedulerBase which
behaved differently in MachineScheduler/PostMachineScheduler. Change
this to let MachineScheduler/PostMachineScheduler just pass in a
parameter to that function.
The order of the LiveIntervals* and bool RemoveKillFlags paramters have
been switched to make out-of-tree code fail instead of unintentionally
passing a value intended for the IsPostRA flag to the (previously
following and default initialized) RemoveKillFlags.
Differential Revision: http://reviews.llvm.org/D14245
llvm-svn: 251883
Diffstat (limited to 'llvm/lib/CodeGen/PostRASchedulerList.cpp')
-rw-r--r-- | llvm/lib/CodeGen/PostRASchedulerList.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 777f77f0dc7..da28d862061 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -196,7 +196,7 @@ SchedulePostRATDList::SchedulePostRATDList( const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs) - : ScheduleDAGInstrs(MF, &MLI, /*IsPostRA=*/true), AA(AA), EndIndex(0) { + : ScheduleDAGInstrs(MF, &MLI), AA(AA), EndIndex(0) { const InstrItineraryData *InstrItins = MF.getSubtarget().getInstrItineraryData(); |