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authorBenjamin Kramer <benny.kra@googlemail.com>2012-02-23 18:28:32 +0000
committerBenjamin Kramer <benny.kra@googlemail.com>2012-02-23 18:28:32 +0000
commit21974b1fa635e40483bba3c785360ce76831f043 (patch)
treeed2149b9dd02030a3095b9bbfc5bc4b34b1fdadf /llvm/lib/CodeGen/PostRASchedulerList.cpp
parent2f0de8bdb93d242e1f6c4ed7c0ecbaaf39bf82ea (diff)
downloadbcm5719-llvm-21974b1fa635e40483bba3c785360ce76831f043.tar.gz
bcm5719-llvm-21974b1fa635e40483bba3c785360ce76831f043.zip
post-ra-sched: Replace a std::set of regs with a bitvector.
Assuming that a single std::set node adds 3 control words, a bitvector can store (3*8+4)*8=224 registers in the allocated memory of a single element in the std::set (x86_64). Also we don't have to call malloc for every register added. llvm-svn: 151269
Diffstat (limited to 'llvm/lib/CodeGen/PostRASchedulerList.cpp')
-rw-r--r--llvm/lib/CodeGen/PostRASchedulerList.cpp9
1 files changed, 4 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp
index e437be1b69a..b3e616e9390 100644
--- a/llvm/lib/CodeGen/PostRASchedulerList.cpp
+++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp
@@ -45,7 +45,6 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/Statistic.h"
-#include <set>
using namespace llvm;
STATISTIC(NumNoops, "Number of noops inserted");
@@ -446,7 +445,7 @@ bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI,
void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
- std::set<unsigned> killedRegs;
+ BitVector killedRegs(TRI->getNumRegs());
BitVector ReservedRegs = TRI->getReservedRegs(MF);
StartBlockForKills(MBB);
@@ -487,7 +486,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
// Examine all used registers and set/clear kill flag. When a
// register is used multiple times we only set the kill flag on
// the first use.
- killedRegs.clear();
+ killedRegs.reset();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isUse()) continue;
@@ -495,7 +494,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
bool kill = false;
- if (killedRegs.find(Reg) == killedRegs.end()) {
+ if (!killedRegs.test(Reg)) {
kill = true;
// A register is not killed if any subregs are live...
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
@@ -519,7 +518,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
DEBUG(MI->dump());
}
- killedRegs.insert(Reg);
+ killedRegs.set(Reg);
}
// Mark any used register (that is not using undef) and subregs as
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