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| author | Gerolf Hoflehner <ghoflehner@apple.com> | 2014-10-14 23:07:53 +0000 |
|---|---|---|
| committer | Gerolf Hoflehner <ghoflehner@apple.com> | 2014-10-14 23:07:53 +0000 |
| commit | a4c96d02a2068a5889b282730e6afa8e1418d1ad (patch) | |
| tree | ec7418e16cb8f0d939f187c1b681f25f2737a0bd /llvm/lib/CodeGen/PeepholeOptimizer.cpp | |
| parent | 1a600faba0329f5cde0aab1ce7bbff2f09252eff (diff) | |
| download | bcm5719-llvm-a4c96d02a2068a5889b282730e6afa8e1418d1ad.tar.gz bcm5719-llvm-a4c96d02a2068a5889b282730e6afa8e1418d1ad.zip | |
[AAarch64] Optimize CSINC-branch sequence
Peephole optimization that generates a single conditional branch
for csinc-branch sequences like in the examples below. This is
possible when the csinc sets or clears a register based on a condition
code and the branch checks that register. Also the condition
code may not be modified between the csinc and the original branch.
Examples:
1. Convert csinc w9, wzr, wzr, <CC>;tbnz w9, #0, 0x44
to b.<invCC>
2. Convert csinc w9, wzr, wzr, <CC>; tbz w9, #0, 0x44
to b.<CC>
rdar://problem/18506500
llvm-svn: 219742
Diffstat (limited to 'llvm/lib/CodeGen/PeepholeOptimizer.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/PeepholeOptimizer.cpp | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp index 7c195a89bd7..90a4dcf8243 100644 --- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp +++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp @@ -135,6 +135,7 @@ namespace { bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB, SmallPtrSetImpl<MachineInstr*> &LocalMIs); bool optimizeSelect(MachineInstr *MI); + bool optimizeCondBranch(MachineInstr *MI); bool optimizeCopyOrBitcast(MachineInstr *MI); bool optimizeCoalescableCopy(MachineInstr *MI); bool optimizeUncoalescableCopy(MachineInstr *MI, @@ -498,6 +499,12 @@ bool PeepholeOptimizer::optimizeSelect(MachineInstr *MI) { return true; } +/// \brief Check if a simpler conditional branch can be +// generated +bool PeepholeOptimizer::optimizeCondBranch(MachineInstr *MI) { + return TII->optimizeCondBranch(MI); +} + /// \brief Check if the registers defined by the pair (RegisterClass, SubReg) /// share the same register file. static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, @@ -1104,6 +1111,11 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &mf) { continue; } + if (MI->isConditionalBranch() && optimizeCondBranch(MI)) { + Changed = true; + continue; + } + if (isCoalescableCopy(*MI) && optimizeCoalescableCopy(MI)) { // MI is just rewritten. Changed = true; |

