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authorFrancis Visoiu Mistrih <francisvm@yahoo.com>2018-01-18 18:05:15 +0000
committerFrancis Visoiu Mistrih <francisvm@yahoo.com>2018-01-18 18:05:15 +0000
commiteb3f76fc83146f85b424a8f923f65263069876dd (patch)
tree151b17a251cc8e20adf951186552f3c261e70662 /llvm/lib/CodeGen/MachineOperand.cpp
parent378b5f3de600ef68d856003454d0e9f3a818762f (diff)
downloadbcm5719-llvm-eb3f76fc83146f85b424a8f923f65263069876dd.tar.gz
bcm5719-llvm-eb3f76fc83146f85b424a8f923f65263069876dd.zip
[CodeGen][NFC] Rename IsVerbose to IsStandalone in Machine*::print
Committed r322867 too soon. Differential Revision: https://reviews.llvm.org/D42239 llvm-svn: 322868
Diffstat (limited to 'llvm/lib/CodeGen/MachineOperand.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineOperand.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index 13af5e11788..9122edefac7 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -641,13 +641,13 @@ void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
const TargetIntrinsicInfo *IntrinsicInfo) const {
tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
ModuleSlotTracker DummyMST(nullptr);
- print(OS, DummyMST, LLT{}, /*PrintDef=*/false, /*IsVerbose=*/true,
+ print(OS, DummyMST, LLT{}, /*PrintDef=*/false, /*IsStandalone=*/true,
/*ShouldPrintRegisterTies=*/true,
/*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
}
void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
- LLT TypeToPrint, bool PrintDef, bool IsVerbose,
+ LLT TypeToPrint, bool PrintDef, bool IsStandalone,
bool ShouldPrintRegisterTies,
unsigned TiedOperandIdx,
const TargetRegisterInfo *TRI,
@@ -687,7 +687,7 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
if (const MachineFunction *MF = getMFIfAvailable(*this)) {
const MachineRegisterInfo &MRI = MF->getRegInfo();
- if (IsVerbose || !PrintDef || MRI.def_empty(Reg)) {
+ if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
OS << ':';
OS << printRegClassOrBank(Reg, MRI, TRI);
}
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