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authorTim Northover <Tim.Northover@arm.com>2012-11-20 09:56:11 +0000
committerTim Northover <Tim.Northover@arm.com>2012-11-20 09:56:11 +0000
commitdd219d06c29793ba03a45f7f08ca844c9f1418f4 (patch)
treeada0b8a0b33cf0de786fc17ec2d3028b20033a0e /llvm/lib/CodeGen/MachineInstrBundle.cpp
parentfc4840fbed6d70083d59c9146dddff3832d18c07 (diff)
downloadbcm5719-llvm-dd219d06c29793ba03a45f7f08ca844c9f1418f4.tar.gz
bcm5719-llvm-dd219d06c29793ba03a45f7f08ca844c9f1418f4.zip
Fix physical register liveness calculations:
+ Take account of clobbers + Give outputs priority over inputs since they happen later. llvm-svn: 168360
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstrBundle.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineInstrBundle.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MachineInstrBundle.cpp b/llvm/lib/CodeGen/MachineInstrBundle.cpp
index 1f7fbfc719b..70f97dedaaa 100644
--- a/llvm/lib/CodeGen/MachineInstrBundle.cpp
+++ b/llvm/lib/CodeGen/MachineInstrBundle.cpp
@@ -281,7 +281,7 @@ MachineOperandIteratorBase::PhysRegInfo
MachineOperandIteratorBase::analyzePhysReg(unsigned Reg,
const TargetRegisterInfo *TRI) {
bool AllDefsDead = true;
- PhysRegInfo PRI = {false, false, false, false, false, false, false};
+ PhysRegInfo PRI = {false, false, false, false, false, false};
assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
"analyzePhysReg not given a physical register!");
@@ -305,7 +305,9 @@ MachineOperandIteratorBase::analyzePhysReg(unsigned Reg,
// Reg or a super-reg is read, and perhaps killed also.
PRI.Reads = true;
PRI.Kills = MO.isKill();
- } if (IsRegOrOverlapping && MO.readsReg()) {
+ }
+
+ if (IsRegOrOverlapping && MO.readsReg()) {
PRI.ReadsOverlap = true;// Reg or an overlapping register is read.
}
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