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authorTim Northover <Tim.Northover@arm.com>2012-11-20 09:56:11 +0000
committerTim Northover <Tim.Northover@arm.com>2012-11-20 09:56:11 +0000
commitdd219d06c29793ba03a45f7f08ca844c9f1418f4 (patch)
treeada0b8a0b33cf0de786fc17ec2d3028b20033a0e /llvm/lib/CodeGen/MachineBasicBlock.cpp
parentfc4840fbed6d70083d59c9146dddff3832d18c07 (diff)
downloadbcm5719-llvm-dd219d06c29793ba03a45f7f08ca844c9f1418f4.tar.gz
bcm5719-llvm-dd219d06c29793ba03a45f7f08ca844c9f1418f4.zip
Fix physical register liveness calculations:
+ Take account of clobbers + Give outputs priority over inputs since they happen later. llvm-svn: 168360
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineBasicBlock.cpp15
1 files changed, 9 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 18d021d521d..4406c89aba2 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -982,7 +982,6 @@ MachineBasicBlock::LivenessQueryResult
MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
unsigned Reg, MachineInstr *MI,
unsigned Neighborhood) {
-
unsigned N = Neighborhood;
MachineBasicBlock *MBB = MI->getParent();
@@ -997,14 +996,18 @@ MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
MachineOperandIteratorBase::PhysRegInfo Analysis =
MIOperands(I).analyzePhysReg(Reg, TRI);
- if (Analysis.Kills)
+ if (Analysis.Defines)
+ // Outputs happen after inputs so they take precedence if both are
+ // present.
+ return Analysis.DefinesDead ? LQR_Dead : LQR_Live;
+
+ if (Analysis.Kills || Analysis.Clobbers)
// Register killed, so isn't live.
return LQR_Dead;
- else if (Analysis.DefinesOverlap || Analysis.ReadsOverlap)
+ else if (Analysis.ReadsOverlap)
// Defined or read without a previous kill - live.
- return (Analysis.Defines || Analysis.Reads) ?
- LQR_Live : LQR_OverlappingLive;
+ return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;
} while (I != MBB->begin() && --N > 0);
}
@@ -1036,7 +1039,7 @@ MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
return (Analysis.Reads) ?
LQR_Live : LQR_OverlappingLive;
- else if (Analysis.DefinesOverlap)
+ else if (Analysis.Clobbers || Analysis.Defines)
// Defined (but not read) therefore cannot have been live.
return LQR_Dead;
}
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