diff options
| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2018-01-18 17:59:06 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2018-01-18 17:59:06 +0000 |
| commit | 378b5f3de600ef68d856003454d0e9f3a818762f (patch) | |
| tree | d51af27d91123c16c85791c4d59e1eab5c093aa1 /llvm/lib/CodeGen/MIRPrinter.cpp | |
| parent | a2d6fe4ab4823e56d01a7cde2cd5eed10f8da960 (diff) | |
| download | bcm5719-llvm-378b5f3de600ef68d856003454d0e9f3a818762f.tar.gz bcm5719-llvm-378b5f3de600ef68d856003454d0e9f3a818762f.zip | |
[CodeGen] Print RegClasses on MI in verbose mode
r322086 removed the trailing information describing reg classes for each
register.
This patch adds printing reg classes next to every register when
individual operands/instructions/basic blocks are printed. In the case
of dumping MIR or printing a full function, by default don't print it.
Differential Revision: https://reviews.llvm.org/D42239
llvm-svn: 322867
Diffstat (limited to 'llvm/lib/CodeGen/MIRPrinter.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MIRPrinter.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index 5e7a2585b4e..5b22762f001 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -768,8 +768,8 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef()) TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx); const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo(); - Op.print(OS, MST, TypeToPrint, PrintDef, ShouldPrintRegisterTies, - TiedOperandIdx, TRI, TII); + Op.print(OS, MST, TypeToPrint, PrintDef, /*IsVerbose=*/false, + ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII); break; } case MachineOperand::MO_FrameIndex: |
