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authorDan Gohman <gohman@apple.com>2008-08-07 02:54:50 +0000
committerDan Gohman <gohman@apple.com>2008-08-07 02:54:50 +0000
commit527ca7e25385090e712946b100d27a786e5d3c8e (patch)
tree603d3f93d455263be8490fda4a41d75086c4e4a5 /llvm/lib/CodeGen/LowerSubregs.cpp
parenta8dbaeb1df09b2200aba9e835513c77c6c6955a3 (diff)
downloadbcm5719-llvm-527ca7e25385090e712946b100d27a786e5d3c8e.tar.gz
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Re-enable elimination of unnecessary SUBREG_TO_REG instructions in
LowerSubregs, and fix an x86-64 isel bug that this exposed. SUBREG_TO_REG for x86-64 implicit zero extension is only safe for isel to generate when the source is known to always have zeros in the high 32 bits. The EXTRACT_SUBREG instruction does not clear the high 32 bits. llvm-svn: 54444
Diffstat (limited to 'llvm/lib/CodeGen/LowerSubregs.cpp')
-rw-r--r--llvm/lib/CodeGen/LowerSubregs.cpp13
1 files changed, 9 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/LowerSubregs.cpp b/llvm/lib/CodeGen/LowerSubregs.cpp
index 1cdd34b77f4..30894ad6ad7 100644
--- a/llvm/lib/CodeGen/LowerSubregs.cpp
+++ b/llvm/lib/CodeGen/LowerSubregs.cpp
@@ -108,15 +108,20 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
DOUT << "subreg: CONVERTING: " << *MI;
- // Insert sub-register copy
- const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
- const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
- TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
+ if (DstSubReg == InsReg) {
+ // No need to insert an identify copy instruction.
+ DOUT << "subreg: eliminated!";
+ } else {
+ // Insert sub-register copy
+ const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
+ const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
+ TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
#ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI;
DOUT << "subreg: " << *(--dMI);
#endif
+ }
DOUT << "\n";
MBB->erase(MI);
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