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authorEvan Cheng <evan.cheng@apple.com>2009-06-15 08:28:29 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-06-15 08:28:29 +0000
commit1283c6a066eb31b2188c5e6810c3b5f948565d44 (patch)
tree6d06bfd58460aaf7c2c423a621f9ce41c74c337c /llvm/lib/CodeGen/LiveInterval.cpp
parent1c0db34815338e612321c65a4f122ea34eed051e (diff)
downloadbcm5719-llvm-1283c6a066eb31b2188c5e6810c3b5f948565d44.tar.gz
bcm5719-llvm-1283c6a066eb31b2188c5e6810c3b5f948565d44.zip
Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
Diffstat (limited to 'llvm/lib/CodeGen/LiveInterval.cpp')
-rw-r--r--llvm/lib/CodeGen/LiveInterval.cpp12
1 files changed, 5 insertions, 7 deletions
diff --git a/llvm/lib/CodeGen/LiveInterval.cpp b/llvm/lib/CodeGen/LiveInterval.cpp
index 97926dd6fd5..4d3ce3a9d43 100644
--- a/llvm/lib/CodeGen/LiveInterval.cpp
+++ b/llvm/lib/CodeGen/LiveInterval.cpp
@@ -507,12 +507,11 @@ void LiveInterval::join(LiveInterval &Other, const int *LHSValNoAssignments,
// Update regalloc hint if currently there isn't one.
if (TargetRegisterInfo::isVirtualRegister(reg) &&
TargetRegisterInfo::isVirtualRegister(Other.reg)) {
- std::pair<MachineRegisterInfo::RegAllocHintType, unsigned> Hint =
- MRI->getRegAllocationHint(reg);
- if (Hint.first == MachineRegisterInfo::RA_None) {
- std::pair<MachineRegisterInfo::RegAllocHintType, unsigned> OtherHint =
+ std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(reg);
+ if (Hint.first == 0 && Hint.second == 0) {
+ std::pair<unsigned, unsigned> OtherHint =
MRI->getRegAllocationHint(Other.reg);
- if (OtherHint.first != MachineRegisterInfo::RA_None)
+ if (OtherHint.first || OtherHint.second)
MRI->setRegAllocationHint(reg, OtherHint.first, OtherHint.second);
}
}
@@ -772,8 +771,7 @@ void LiveInterval::Copy(const LiveInterval &RHS,
BumpPtrAllocator &VNInfoAllocator) {
ranges.clear();
valnos.clear();
- std::pair<MachineRegisterInfo::RegAllocHintType, unsigned> Hint =
- MRI->getRegAllocationHint(RHS.reg);
+ std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(RHS.reg);
MRI->setRegAllocationHint(reg, Hint.first, Hint.second);
weight = RHS.weight;
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