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authorMarina Yatsina <marina.yatsina@intel.com>2016-07-21 12:37:07 +0000
committerMarina Yatsina <marina.yatsina@intel.com>2016-07-21 12:37:07 +0000
commitc1fa163392f52d2119dec645f4f127ef79b83310 (patch)
tree2f6985de132bf3468ddc1354f9a9e48ac4ee3173 /llvm/lib/CodeGen/ExecutionDepsFix.cpp
parent2a185a2547caccd5e969e2c5e704ee9733aaa2fc (diff)
downloadbcm5719-llvm-c1fa163392f52d2119dec645f4f127ef79b83310.tar.gz
bcm5719-llvm-c1fa163392f52d2119dec645f4f127ef79b83310.zip
ExecutionDepsFix - Fix bug in clearance calculation
The clearance calculation did not take into account registers defined as outputs or clobbers in inline assembly machine instructions because these register defs are implicit. Differential Revision: http://reviews.llvm.org/D22580 llvm-svn: 276266
Diffstat (limited to 'llvm/lib/CodeGen/ExecutionDepsFix.cpp')
-rw-r--r--llvm/lib/CodeGen/ExecutionDepsFix.cpp2
1 files changed, 0 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/ExecutionDepsFix.cpp b/llvm/lib/CodeGen/ExecutionDepsFix.cpp
index 566b8d507b2..1fe5f459b69 100644
--- a/llvm/lib/CodeGen/ExecutionDepsFix.cpp
+++ b/llvm/lib/CodeGen/ExecutionDepsFix.cpp
@@ -520,8 +520,6 @@ void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg())
continue;
- if (MO.isImplicit())
- break;
if (MO.isUse())
continue;
for (int rx : regIndices(MO.getReg())) {
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