diff options
author | Andrew Trick <atrick@apple.com> | 2012-03-07 23:01:09 +0000 |
---|---|---|
committer | Andrew Trick <atrick@apple.com> | 2012-03-07 23:01:09 +0000 |
commit | 69b4204c18d0b91ae3b66b4f580c49441f38f444 (patch) | |
tree | cdf901568fb84b3243854b4be7b37dafcf1a6692 /llvm/lib/CodeGen/DFAPacketizer.cpp | |
parent | 9a0c583954fb0edbce7375dda7c3f36c80cea928 (diff) | |
download | bcm5719-llvm-69b4204c18d0b91ae3b66b4f580c49441f38f444.tar.gz bcm5719-llvm-69b4204c18d0b91ae3b66b4f580c49441f38f444.zip |
Cleanup VLIWPacketizer to use the updated ScheduleDAGInstrs interface.
llvm-svn: 152262
Diffstat (limited to 'llvm/lib/CodeGen/DFAPacketizer.cpp')
-rw-r--r-- | llvm/lib/CodeGen/DFAPacketizer.cpp | 30 |
1 files changed, 12 insertions, 18 deletions
diff --git a/llvm/lib/CodeGen/DFAPacketizer.cpp b/llvm/lib/CodeGen/DFAPacketizer.cpp index 3d178c76f97..5ff641c7c84 100644 --- a/llvm/lib/CodeGen/DFAPacketizer.cpp +++ b/llvm/lib/CodeGen/DFAPacketizer.cpp @@ -103,9 +103,6 @@ void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) { namespace { // DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides // Schedule method to build the dependence graph. -// -// ScheduleDAGInstrs has LLVM_LIBRARY_VISIBILITY so we have to reference it as -// an opaque pointer in VLIWPacketizerList. class DefaultVLIWScheduler : public ScheduleDAGInstrs { public: DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI, @@ -137,7 +134,7 @@ VLIWPacketizerList::VLIWPacketizerList( // VLIWPacketizerList Dtor VLIWPacketizerList::~VLIWPacketizerList() { - delete (DefaultVLIWScheduler *)SchedulerImpl; + delete SchedulerImpl; delete ResourceTracker; } @@ -184,20 +181,15 @@ void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB, void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB, MachineBasicBlock::iterator BeginItr, MachineBasicBlock::iterator EndItr) { - DefaultVLIWScheduler *Scheduler = (DefaultVLIWScheduler *)SchedulerImpl; - Scheduler->enterRegion(MBB, BeginItr, EndItr, MBB->size()); - Scheduler->schedule(); - Scheduler->exitRegion(); + assert(MBB->end() == EndItr && "Bad EndIndex"); - // Remember scheduling units. - SUnits = Scheduler->SUnits; + SchedulerImpl->enterRegion(MBB, BeginItr, EndItr, MBB->size()); - // Generate MI -> SU map. - std::map <MachineInstr*, SUnit*> MIToSUnit; - for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { - SUnit *SU = &SUnits[i]; - MIToSUnit[SU->getInstr()] = SU; - } + // Build the DAG without reordering instructions. + SchedulerImpl->schedule(); + + // Remember scheduling units. + SUnits = SchedulerImpl->SUnits; // The main packetizer loop. for (; BeginItr != EndItr; ++BeginItr) { @@ -213,7 +205,7 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB, continue; } - SUnit *SUI = MIToSUnit[MI]; + SUnit *SUI = SchedulerImpl->getSUnit(MI); assert(SUI && "Missing SUnit Info!"); // Ask DFA if machine resource is available for MI. @@ -223,7 +215,7 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB, for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end(); VI != VE; ++VI) { MachineInstr *MJ = *VI; - SUnit *SUJ = MIToSUnit[MJ]; + SUnit *SUJ = SchedulerImpl->getSUnit(MJ); assert(SUJ && "Missing SUnit Info!"); // Is it legal to packetize SUI and SUJ together. @@ -247,4 +239,6 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB, // End any packet left behind. endPacket(MBB, EndItr); + + SchedulerImpl->exitRegion(); } |