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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-21 02:37:33 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-21 02:37:33 +0000 |
| commit | eb6eb694e42d85541a1abc79f6025425540f8a7c (patch) | |
| tree | 25fb26a6d0949fdf5cba10ecfdf3663242344454 /llvm/lib/CodeGen/CallingConvLower.cpp | |
| parent | bd7f2354ccbaa50923b134b223349ae532443aba (diff) | |
| download | bcm5719-llvm-eb6eb694e42d85541a1abc79f6025425540f8a7c.tar.gz bcm5719-llvm-eb6eb694e42d85541a1abc79f6025425540f8a7c.zip | |
AMDGPU/GlobalISel: Allow selection of scalar min/max
I believe all of the uniform/divergent pattern predicates are
redundant and can be removed. The uniformity bit already influences
the register class, and nothhing has broken when I've removed this and
others.
llvm-svn: 372450
Diffstat (limited to 'llvm/lib/CodeGen/CallingConvLower.cpp')
0 files changed, 0 insertions, 0 deletions
