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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-06-16 21:43:12 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-06-16 21:43:12 +0000 |
| commit | 8dad57cc49f2463356210016b9a692611082b656 (patch) | |
| tree | 8089e615a1a1288dfaedd5f15f85c30b1c9e5bca /llvm/lib/Analysis | |
| parent | f9e890cbf964ec2222693034d159c49a28f6f117 (diff) | |
| download | bcm5719-llvm-8dad57cc49f2463356210016b9a692611082b656.tar.gz bcm5719-llvm-8dad57cc49f2463356210016b9a692611082b656.zip | |
TTI: Add hook for memory width to vectorize
llvm-svn: 272964
Diffstat (limited to 'llvm/lib/Analysis')
| -rw-r--r-- | llvm/lib/Analysis/TargetTransformInfo.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index 8e9252ce662..155a698c399 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -224,6 +224,10 @@ unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const { return TTIImpl->getRegisterBitWidth(Vector); } +unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const { + return TTIImpl->getLoadStoreVecRegBitWidth(AS); +} + unsigned TargetTransformInfo::getCacheLineSize() const { return TTIImpl->getCacheLineSize(); } |
