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authorBhushan D. Attarde <Bhushan.Attarde@imgtec.com>2015-10-06 08:52:08 +0000
committerBhushan D. Attarde <Bhushan.Attarde@imgtec.com>2015-10-06 08:52:08 +0000
commitf55a0a47cf419a5e9de9ab13b83ae3b664ce4401 (patch)
treeca0fd0dd96a169e1fc6b52b60a7bfaac0b879b19 /lldb/scripts/Python
parent15f2bd9549247a7b8f3e651e7f51497aaaea50bd (diff)
downloadbcm5719-llvm-f55a0a47cf419a5e9de9ab13b83ae3b664ce4401.tar.gz
bcm5719-llvm-f55a0a47cf419a5e9de9ab13b83ae3b664ce4401.zip
[MIPS] Emulate microMIPS instructions
SUMMARY: This patch includes: 1. Emulation of prologue/epilogue and branch instructions for microMIPS. 2. Setting up alternate disassembler (to be used for microMIPS). So there will be two disassembler instances, one for microMIPS and other for MIPS. Appropriate disassembler will be used based on the address class of instruction address. 3. Some of the branch instructions does not have fixed sized delay slot, that means delay slot instruction can be of 2-byte or 4-byte. For this "m_next_inst_size" has been introduced which stores the size of next instruction (i.e size of delay slot instruction in case of branch). This can be used wherever the size of next instruction is required. 4. A minor change to use mips32 register names instead of mips64 names. Reviewers: clayborg, tberghammer Subscribers: mohit.bhakkad, sagar, jaydeep, nitesh.jain, lldb-commits Differential Revision: http://reviews.llvm.org/D13282 llvm-svn: 249381
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