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| author | Alex Bradbury <asb@lowrisc.org> | 2017-12-11 11:53:54 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-12-11 11:53:54 +0000 |
| commit | 660bcceccf85bfc2bbac4f28b87e94c1f3e82184 (patch) | |
| tree | f912cc41c2b4669b0c611f253189434ef857902d /lldb/packages/Python/lldbsuite/test/python_api/signals/main.cpp | |
| parent | 775bb7437932ea6141c33ab63074640fb541997e (diff) | |
| download | bcm5719-llvm-660bcceccf85bfc2bbac4f28b87e94c1f3e82184.tar.gz bcm5719-llvm-660bcceccf85bfc2bbac4f28b87e94c1f3e82184.zip | |
[RISCV] Support lowering FrameIndex
Introduces the AddrFI "addressing mode", which is necessary simply because
it's not possible to write a pattern that directly matches a frameindex.
Ensure callee-saved registers are accessed relative to the stackpointer. This
is necessary as callee-saved register spills are performed before the frame
pointer is set.
Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can
make use of it in the RISC-V backend.
Differential Revision: https://reviews.llvm.org/D39848
llvm-svn: 320353
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/signals/main.cpp')
0 files changed, 0 insertions, 0 deletions
