[ELF][RISCV] Support GD/LD/IE/LE TLS models

RISC-V psABI doesn't specify TLS relaxation. It can be handled the same
way as we handle ARM TLS. RISC-V TLS is even simpler because GD/LD use
the same relocation type.

Reviewed By: jrtc27, ruiu

Differential Revision: https://reviews.llvm.org/D63220

llvm-svn: 364813

1 files changed, 4 insertions, 1 deletions

diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp
index 397bb84a6f9..7fc7b011602 100644
--- a/lld/ELF/InputSection.cpp
+++ b/lld/ELF/InputSection.cpp
@@ -587,7 +587,8 @@ static Relocation *getRISCVPCRelHi20(const Symbol *Sym, uint64_t Addend) {
                        });
 
   for (auto It = Range.first; It != Range.second; ++It)
-    if (It->Type == R_RISCV_PCREL_HI20 || It->Type == R_RISCV_GOT_HI20)
+    if (It->Type == R_RISCV_PCREL_HI20 || It->Type == R_RISCV_GOT_HI20 ||
+        It->Type == R_RISCV_TLS_GD_HI20 || It->Type == R_RISCV_TLS_GOT_HI20)
       return &*It;
 
   error("R_RISCV_PCREL_LO12 relocation points to " + IS->getObjMsg(D->Value) +
@@ -620,6 +621,8 @@ static int64_t getTlsTpOffset(const Symbol &S) {
     // offset to reach 0x1000 of TCB/thread-library data and 0xf000 of the
     // program's TLS segment.
     return S.getVA(0) - 0x7000;
+  case EM_RISCV:
+    return S.getVA(0);
   default:
     llvm_unreachable("unhandled Config->EMachine");
   }