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| author | Tim Northover <tnorthover@apple.com> | 2014-03-12 11:29:23 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-03-12 11:29:23 +0000 |
| commit | 3cccc45a9f7f341d5ef4d866ba20ce16521e0e27 (patch) | |
| tree | 7f68af884e99de4581bce77189b9f366bf83d685 /clang/test/CodeGen/cxx-condition.cpp | |
| parent | 487767cfc8fc74a61dc593ff7e96120e037ab7f5 (diff) | |
| download | bcm5719-llvm-3cccc45a9f7f341d5ef4d866ba20ce16521e0e27.tar.gz bcm5719-llvm-3cccc45a9f7f341d5ef4d866ba20ce16521e0e27.zip | |
ARM: correct Dwarf output for non-contiguous VFP saves.
When the list of VFP registers to be saved was non-contiguous (so multiple
vpush/vpop instructions were needed) these were being ordered oddly, as in:
vpush {d8, d9}
vpush {d11}
This led to the layout in memory being [d11, d8, d9] which is ugly and doesn't
match the CFI_INSTRUCTIONs we're generating either (so Dwarf info would be
broken).
This switches the order of vpush/vpop (in both prologue and epilogue,
obviously) so that the Dwarf locations are correct again.
rdar://problem/16264856
llvm-svn: 203655
Diffstat (limited to 'clang/test/CodeGen/cxx-condition.cpp')
0 files changed, 0 insertions, 0 deletions
