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| author | Eric Christopher <echristo@gmail.com> | 2014-12-18 02:08:55 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@gmail.com> | 2014-12-18 02:08:55 +0000 |
| commit | 560cc4fb44e11c0153f985639375598b53831e18 (patch) | |
| tree | 5411494cdcbf8d64dbd0a26164718661e1dcd5b3 /clang/test/CodeGen/atomics-inlining.c | |
| parent | 7a8b31d631acb9c1b7b1e654fcbfd476ac502c0f (diff) | |
| download | bcm5719-llvm-560cc4fb44e11c0153f985639375598b53831e18.tar.gz bcm5719-llvm-560cc4fb44e11c0153f985639375598b53831e18.zip | |
Make sure that arm-linux-gnu is still the apcs-gnu ABI when we
use clang -cc1 matching the front end and backend. Fix up a couple
of tests that were testing aapcs for arm-linux-gnu.
The test that removes the aapcs abi calling convention removes
them because the default triple matches what the backend uses
for the calling convention there and so it doesn't need to be
explicitly stated - see the code in TargetInfo.cpp.
llvm-svn: 224491
Diffstat (limited to 'clang/test/CodeGen/atomics-inlining.c')
| -rw-r--r-- | clang/test/CodeGen/atomics-inlining.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/clang/test/CodeGen/atomics-inlining.c b/clang/test/CodeGen/atomics-inlining.c index ec916e1b5ee..9cd280294f3 100644 --- a/clang/test/CodeGen/atomics-inlining.c +++ b/clang/test/CodeGen/atomics-inlining.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=ARM +// RUN: %clang_cc1 -triple arm-linux-gnueabi -emit-llvm %s -o - | FileCheck %s -check-prefix=ARM // RUN: %clang_cc1 -triple powerpc-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=PPC32 // RUN: %clang_cc1 -triple powerpc64-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=PPC64 // RUN: %clang_cc1 -triple mipsel-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS32 @@ -31,17 +31,17 @@ void test1(void) { (void)__atomic_load(&a1, &a2, memory_order_seq_cst); (void)__atomic_store(&a1, &a2, memory_order_seq_cst); -// ARM-LABEL: define arm_aapcscc void @test1 -// ARM: = call arm_aapcscc zeroext i8 @__atomic_load_1(i8* @c1 -// ARM: call arm_aapcscc void @__atomic_store_1(i8* @c1, i8 zeroext -// ARM: = call arm_aapcscc zeroext i16 @__atomic_load_2(i8* bitcast (i16* @s1 to i8*) -// ARM: call arm_aapcscc void @__atomic_store_2(i8* bitcast (i16* @s1 to i8*), i16 zeroext -// ARM: = call arm_aapcscc i32 @__atomic_load_4(i8* bitcast (i32* @i1 to i8*) -// ARM: call arm_aapcscc void @__atomic_store_4(i8* bitcast (i32* @i1 to i8*), i32 -// ARM: = call arm_aapcscc i64 @__atomic_load_8(i8* bitcast (i64* @ll1 to i8*) -// ARM: call arm_aapcscc void @__atomic_store_8(i8* bitcast (i64* @ll1 to i8*), i64 -// ARM: call arm_aapcscc void @__atomic_load(i32 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0) -// ARM: call arm_aapcscc void @__atomic_store(i32 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0) +// ARM-LABEL: define{{.*}} void @test1 +// ARM: = call{{.*}} zeroext i8 @__atomic_load_1(i8* @c1 +// ARM: call{{.*}} void @__atomic_store_1(i8* @c1, i8 zeroext +// ARM: = call{{.*}} zeroext i16 @__atomic_load_2(i8* bitcast (i16* @s1 to i8*) +// ARM: call{{.*}} void @__atomic_store_2(i8* bitcast (i16* @s1 to i8*), i16 zeroext +// ARM: = call{{.*}} i32 @__atomic_load_4(i8* bitcast (i32* @i1 to i8*) +// ARM: call{{.*}} void @__atomic_store_4(i8* bitcast (i32* @i1 to i8*), i32 +// ARM: = call{{.*}} i64 @__atomic_load_8(i8* bitcast (i64* @ll1 to i8*) +// ARM: call{{.*}} void @__atomic_store_8(i8* bitcast (i64* @ll1 to i8*), i64 +// ARM: call{{.*}} void @__atomic_load(i32 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0) +// ARM: call{{.*}} void @__atomic_store(i32 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0) // PPC32-LABEL: define void @test1 // PPC32: = load atomic i8* @c1 seq_cst |
