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authorDaniel Dunbar <daniel@zuster.org>2010-08-11 02:17:20 +0000
committerDaniel Dunbar <daniel@zuster.org>2010-08-11 02:17:20 +0000
commit9034aa36c78a01e3d440bf4fe2cd8c0f2f6da7cb (patch)
treeed8a91a1d6e708a93b02d76672a993eef8d0ae3b /clang/test/CodeGen/asm_arm.c
parent256e1f3ad05d6ffe89f7e64a65ee5e753ddb228c (diff)
downloadbcm5719-llvm-9034aa36c78a01e3d440bf4fe2cd8c0f2f6da7cb.tar.gz
bcm5719-llvm-9034aa36c78a01e3d440bf4fe2cd8c0f2f6da7cb.zip
ARM: Recognize single precision float register names.
- We don't recognize double or NEON register names yet -- we don't have the infrastructure to generate the right clobbers for them. llvm-svn: 110775
Diffstat (limited to 'clang/test/CodeGen/asm_arm.c')
-rw-r--r--clang/test/CodeGen/asm_arm.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/clang/test/CodeGen/asm_arm.c b/clang/test/CodeGen/asm_arm.c
index 12cf5d79c83..633bf5569dd 100644
--- a/clang/test/CodeGen/asm_arm.c
+++ b/clang/test/CodeGen/asm_arm.c
@@ -38,3 +38,17 @@ void test4(float *a, float *b) {
void test5() {
__asm__("" : : : "r13", "r14", "r15", "sp", "lr", "pc");
}
+
+// CHECK: @test6
+// CHECK: call void asm sideeffect "", "
+// CHECK: ~{s0},~{s1},~{s2},~{s3},~{s4},~{s5},~{s6},~{s7},
+// CHECK: ~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},
+// CHECK: ~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},
+// CHECK: ~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"()
+void test6() {
+ __asm__("" : : :
+ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+ "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
+ "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
+ "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31");
+}
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