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authorDavid Green <david.green@arm.com>2019-07-15 11:35:39 +0000
committerDavid Green <david.green@arm.com>2019-07-15 11:35:39 +0000
commit6e89887642f4eca39a8e2339adb32c176aa67ce9 (patch)
tree8d475b14e75fbd30a3547d7abc5949d0d9fc5e37 /clang/lib/CodeGen/CodeGenModule.cpp
parent0bf0b8ff7c7edcad0f79e4c39dddd58bc0d62a72 (diff)
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[ARM] MVE Vector Shifts
This adds basic lowering for MVE shifts. There are many shifts in MVE, but the instructions handled here are: VSHL (imm) VSHRu (imm) VSHRs (imm) VSHL (vector) VSHL (register) MVE, like NEON before it, doesn't have shift right by a vector (or register). We instead have to negate the amount and shift in the opposite direction. This means we have to convert any SHR's into a form of SHL (that is still signed or unsigned) with a negated condition and selecting from there. MVE still does have shifting by an immediate for SHL, ASR and LSR. This adds lowering for these and for register forms, which work well for shift lefts but may require an extra fold of neg(vdup(x)) -> vdup(neg(x)) to potentially work optimally for right shifts. Differential Revision: https://reviews.llvm.org/D64212 llvm-svn: 366056
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