summaryrefslogtreecommitdiffstats
path: root/clang/lib/CodeGen/CodeGenModule.cpp
diff options
context:
space:
mode:
authorSanjay Patel <spatel@rotateright.com>2017-07-08 14:04:48 +0000
committerSanjay Patel <spatel@rotateright.com>2017-07-08 14:04:48 +0000
commit18ee908ca2a5f797261d8b75de5cdf74a4f863e7 (patch)
tree6564b9c8bc1dfa6554a77245f367c684f6490a93 /clang/lib/CodeGen/CodeGenModule.cpp
parentcbf647cc3a712ada34fcd78f7d39756193f323d2 (diff)
downloadbcm5719-llvm-18ee908ca2a5f797261d8b75de5cdf74a4f863e7.tar.gz
bcm5719-llvm-18ee908ca2a5f797261d8b75de5cdf74a4f863e7.zip
[x86] add SBB optimization for SETBE (ule) condition code
x86 scalar select-of-constants (Cond ? C1 : C2) combining/lowering is a mess with missing optimizations. We handle some patterns, but miss logical variants. To clean that up, we should convert all select-of-constants to logic/math and enhance the combining for the expected patterns from that. Selecting 0 or -1 needs extra attention to produce the optimal code as shown here. Attempt to verify that all of these IR forms are logically equivalent: http://rise4fun.com/Alive/plxs Earlier steps in this series: rL306040 rL306072 rL307404 (D34652) As acknowledged in the earlier review, there's a possibility that some Intel uarch would prefer to produce an xor to clear the fake register operand with sbb %eax, %eax. This will likely need to be addressed in a separate pass. llvm-svn: 307471
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions
OpenPOWER on IntegriCloud