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| author | Tim Northover <tnorthover@apple.com> | 2013-05-30 10:43:18 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-05-30 10:43:18 +0000 |
| commit | 04eb4234fcfb1985c8d90cdcaa66e88dfe97edb4 (patch) | |
| tree | 3403485997c662ca3f197255905b2848bdc3ac8a /clang/lib/CodeGen/CodeGenFunction.cpp | |
| parent | 46af5a2cdc7e1386884c3260e05f1e7164fe33c0 (diff) | |
| download | bcm5719-llvm-04eb4234fcfb1985c8d90cdcaa66e88dfe97edb4.tar.gz bcm5719-llvm-04eb4234fcfb1985c8d90cdcaa66e88dfe97edb4.zip | |
X86: change zext moves to use sub-register infrastructure.
32-bit writes on amd64 zero out the high bits of the corresponding 64-bit
register. LLVM makes use of this for zero-extension, but until now relied on
custom MCLowering and other code to fixup instructions. Now we have proper
handling of sub-registers, this can be done by creating SUBREG_TO_REG
instructions at selection-time.
Should be no change in functionality.
llvm-svn: 182921
Diffstat (limited to 'clang/lib/CodeGen/CodeGenFunction.cpp')
0 files changed, 0 insertions, 0 deletions
