summaryrefslogtreecommitdiffstats
path: root/clang/lib/Basic/Targets/RISCV.cpp
diff options
context:
space:
mode:
authorAlex Bradbury <asb@lowrisc.org>2019-07-18 15:33:41 +0000
committerAlex Bradbury <asb@lowrisc.org>2019-07-18 15:33:41 +0000
commitfc3aa2ab485fdfb2859365ce12e6154b918c639c (patch)
treec878b081e6efb881505a05c6e51bc47215c55361 /clang/lib/Basic/Targets/RISCV.cpp
parentd2c576110ef52da573f6dafd5ef268bde5ef5999 (diff)
downloadbcm5719-llvm-fc3aa2ab485fdfb2859365ce12e6154b918c639c.tar.gz
bcm5719-llvm-fc3aa2ab485fdfb2859365ce12e6154b918c639c.zip
[RISCV] Hard float ABI support
The RISC-V hard float calling convention requires the frontend to: * Detect cases where, once "flattened", a struct can be passed using int+fp or fp+fp registers under the hard float ABI and coerce to the appropriate type(s) * Track usage of GPRs and FPRs in order to gate the above, and to determine when signext/zeroext attributes must be added to integer scalars This patch attempts to do this in compliance with the documented ABI, and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as author of that code I've tagged you as reviewer for initial feedback on my usage. Note that a previous version of the ABI indicated that when passing an int+fp struct using a GPR+FPR, the int would need to be sign or zero-extended appropriately. GCC never did this and the ABI was changed, which makes life easier as ABIArgInfo::CoerceAndExpand can't currently handle sign/zero-extension attributes. Differential Revision: https://reviews.llvm.org/D60456 llvm-svn: 366450
Diffstat (limited to 'clang/lib/Basic/Targets/RISCV.cpp')
-rw-r--r--clang/lib/Basic/Targets/RISCV.cpp13
1 files changed, 11 insertions, 2 deletions
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index f800bb0b25d..58272d14abd 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -65,9 +65,18 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__riscv");
bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32");
- // TODO: modify when more code models and ABIs are supported.
+ // TODO: modify when more code models are supported.
Builder.defineMacro("__riscv_cmodel_medlow");
- Builder.defineMacro("__riscv_float_abi_soft");
+
+ StringRef ABIName = getABI();
+ if (ABIName == "ilp32f" || ABIName == "lp64f")
+ Builder.defineMacro("__riscv_float_abi_single");
+ else if (ABIName == "ilp32d" || ABIName == "lp64d")
+ Builder.defineMacro("__riscv_float_abi_double");
+ else if (ABIName == "ilp32e")
+ Builder.defineMacro("__riscv_abi_rve");
+ else
+ Builder.defineMacro("__riscv_float_abi_soft");
if (HasM) {
Builder.defineMacro("__riscv_mul");
OpenPOWER on IntegriCloud