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| author | Simon Atanasyan <simon@atanasyan.com> | 2019-11-05 10:31:16 +0300 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-11-05 12:10:58 +0300 |
| commit | e578d0fd295a67bce1e1fc922237f459deb49c7e (patch) | |
| tree | 8d8f6cd93f99e2d41f91325b7a1a207f4ecbcfd5 /clang/lib/Basic/Targets/Mips.cpp | |
| parent | 92164cf25d513d44fdb5d727a33d02ad4c87384e (diff) | |
| download | bcm5719-llvm-e578d0fd295a67bce1e1fc922237f459deb49c7e.tar.gz bcm5719-llvm-e578d0fd295a67bce1e1fc922237f459deb49c7e.zip | |
[mips] Fix `__mips_isa_rev` macros value for Octeon CPU
Diffstat (limited to 'clang/lib/Basic/Targets/Mips.cpp')
| -rw-r--r-- | clang/lib/Basic/Targets/Mips.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp index 2cafbe87a99..4ca7f08af82 100644 --- a/clang/lib/Basic/Targets/Mips.cpp +++ b/clang/lib/Basic/Targets/Mips.cpp @@ -61,7 +61,7 @@ void MipsTargetInfo::fillValidCPUList( unsigned MipsTargetInfo::getISARev() const { return llvm::StringSwitch<unsigned>(getCPU()) .Cases("mips32", "mips64", 1) - .Cases("mips32r2", "mips64r2", 2) + .Cases("mips32r2", "mips64r2", "octeon", 2) .Cases("mips32r3", "mips64r3", 3) .Cases("mips32r5", "mips64r5", 5) .Cases("mips32r6", "mips64r6", 6) |
